1. Field of the Invention
Generally, the present disclosure relates to the formation of integrated circuits, and, more particularly, to patterning dielectric materials in semiconductor devices by means of sophisticated lithography techniques using appropriate anti-reflective coating (ARC) layers.
2. Description of the Related Art
In modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby steadily increasing the performance of these circuits in terms of speed and/or power consumption. As the size of the individual circuit elements is significantly reduced, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines have to be reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per chip.
During the manufacturing process for forming respective wiring layers of semiconductor devices, frequently respective dielectric materials may have to be patterned to receive appropriate openings, which are filled with a conductive material to establish an electrical connection with circuit elements located in the device layer of the semiconductor device. Hence, the patterning of these openings requires highly sophisticated lithography processes, since the minimal dimensions of respective openings may be comparable with the resolution capability of modern lithography systems. In a sophisticated photolithography process, a resist material of well-defined photochemical characteristics with respect to the exposure wavelength under consideration is selectively exposed on the basis of a reticle to generate a latent image in the resist material, which, after developing the latent image, may be used as a mask for patterning a material layer formed below the resist mask. The continuous drive for smaller feature sizes requires reduced exposure wavelengths to be used for the imaging process, since the resolution of the optical system depends on, among other things, the wavelength of the exposure light. Hence, the corresponding resist materials also have to be adapted to the shorter exposure wavelength, while additionally the corresponding layer thickness of the resist material has to be reduced to comply with the respective absorption lengths obtained for the specified wavelengths within the resist material. For a precise generation of a latent image in the resist material, i.e., the precise deposition of energy above a well-defined threshold, interfering reflections of the exposure light at interfaces of different layers formed below the resist material have to be reduced as much as possible. For this reason, respective anti-reflective coating (ARC) layers may have to be provided, whose optical characteristics are tailored with respect to the incoming exposure wavelength so as to minimize the back reflection of light after passing through the resist material. Hence, for a given exposure wavelength and a specified process sequence, dedicated ARC materials are provided with a specific thickness and material composition to obtain a desired index of refraction and extinction coefficient. For example, nitrogen-enriched silicon dioxide is a frequently used ARC material, since the optical characteristics thereof may be readily adjusted by varying the amount of oxygen and nitrogen during the deposition of the layer.
A further problem in patterning material layers on the basis of sophisticated resist materials for short exposure wavelength has been underestimated in the past and is now considered a major challenge in the patterning of dielectrics, such as the formation of contact plugs and vias of metallization structures. After the exposure the resist materials and during developing the photoresist, certain portions of the resist, which have been properly exposed, may, however, not be completely removed as required and thus the structure may then not be correctly transferred into the underlying dielectric material during the subsequent etch process. The effect of insufficiently exposing and developing the photoresist is also referred to as resist poisoning. It is believed that a significant change of the resist sensitivity may be caused by an interaction of nitrogen and nitrogen radicals with the resist layer, thereby locally blocking the photo acidic generator effect during exposure and post-exposure bake of the resist and thus locally modifying the resist structure after resist development.
The problem is becoming even more important as the wavelength of the lithography used is reduced as a consequence of more sophisticated process requirements. For instance, currently the patterning of critical features sizes of cutting edge devices may be performed on the basis of a 193 nm light source, requiring appropriately designed photoresists that are highly sensitive in this wavelength range. It turns out, however, that, with increased sensitivity at shorter wavelengths, the available photoresists also exhibit an increased sensitivity for resist poisoning mechanisms. Since the introduction of the 90 nm technology and beyond may also require a correspondingly advanced lithography process in the formation of metallization structures contacting the circuit elements, increased problems may occur during the patterning of the dielectric as nitrogen and/or compounds may be present in well-approved ARC materials comprised of silicon oxynitride (SiON) and other layers in the layer stack. It is therefore usually necessary to provide a cap layer for the ARC material providing sufficient protection against undue nitrogen contamination of the resist material, while on the other hand not unduly affecting the optical behavior of the actual ARC material. For example, silicon dioxide may be efficiently used as a cap material, wherein a thickness thereof may be specifically designed with respect to the ARC material and also with respect to other criteria in view of process compatibility with preceding and subsequent processes, such as resist strip, etching and the like.
Moreover, due to the complexity of the entire patterning process sequence, including the process for forming the ARC layer including the cap layer, the resist coating and processing, the lithography process and the etching including the resist strip and the like, a high process efficiency, not only in view of yield but also in view of throughput, is highly desirable to reduce the overall production costs. In this respect, the ARC stack comprising the silicon oxynitride (SiON) and the SiO material is highly advantageous, since it may be formed in a single deposition chamber on the basis of well-established process parameters.
It appears, however, that the overall process yield may be reduced due to a moderately high defect rate, which may even increase during the course of processing a plurality of substrates. With reference to FIGS. 1a-1d, a typical conventional process flow will now be described in more detail to illustrate the problems associated therewith.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100, which may comprise a substrate 101, such as a silicon substrate, a silicon-on-insulator (SOI) substrate and the like. Furthermore, the substrate 101 may have formed thereon respective circuit elements, which may commonly be referred to as 102, that may represent semiconductor devices, such as transistors, capacitors and the like or other conductive regions. As an example, a single contact area 103 of a transistor element, such as a drain or source region or a contact area of a gate electrode, is shown in FIG. 1a. 
The semiconductor device 100 may further comprise an interlayer dielectric material 104, which may dielectrically isolate circuit elements from each other, wherein the interlayer dielectric material 104 may be comprised of a first layer 104A, acting as an etch stop layer, and a second layer 104B, which may represent the actual dielectric material providing the desired electrical and mechanical characteristics. For example, in sophisticated applications, the etch stop layer 104A may be comprised of silicon nitride, for instance exhibiting a high intrinsic stress, while the layer 104B may be comprised of silicon dioxide formed on the basis of high density plasma chemical vapor deposition, sub-atmospheric chemical vapor deposition on the basis of TEOS and the like. Since the interlayer dielectric material 104 has to be patterned so as to receive a corresponding contact opening for connecting to the contact area 103, which may represent a circuit feature of highly scaled lateral dimensions, a sophisticated patterning process sequence also has to be employed for patterning the material 104 as previously explained.
Hence, an efficient anti-reflecting coating (ARC) 105 is formed on the interlayer dielectric material 104, wherein the ARC 105 is comprised of a first layer 105A, which provides the required optical characteristics, i.e., a high degree of absorption in order to avoid unwanted back reflection into an overlying resist mask 106. As previously explained, silicon oxynitride (SiON) may be advantageously used, wherein the respective optical characteristics may be defined by the ratio of the corresponding oxygen and nitrogen species. Furthermore, the ARC 105 may comprise a cap layer 105B comprised of silicon dioxide in order to avoid undue nitrogen contamination of the resist mask 106. Typically, the thickness of the cap layer 105B is significantly less compared to the thickness of the actual ARC material of the layer 105A, wherein, for instance, in sophisticated applications necessitating an exposure wavelength of 248 nm or even 193 nm, a thickness of the layer 105A is in the range of several tenths of nanometers, while a thickness of the cap layer 105B is 10 nm and even less. Moreover, in this manufacturing stage, a respective opening 106A is formed in the resist mask 106 so as to substantially represent the corresponding lateral dimensions of a corresponding contact opening to be formed in the interlayer dielectric material 104.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1a may comprise the following processes. After manufacturing the respective circuit elements 102, including the contact area 103, on the basis of well-established techniques, the interlayer dielectric material 104 may be deposited by first providing the contact etch stop layer 104A on the basis of well established plasma enhanced chemical vapor deposition (PECVD) techniques, followed by the deposition of the silicon dioxide material as previously described. Thereafter, the surface topography of the material 104 may be planarized, if required, in order to provide enhanced surface conditions for the subsequent patterning of the material 104. Thereafter, the ARC 105 may be formed in a combined process, wherein, in a first deposition step, the respective process parameters may be controlled such that a desired material composition of the silicon oxynitride is maintained, wherein substantially pure silicon dioxide may be subsequently deposited in order to form the cap layer 105B having the required low thickness so as to not unduly influence the optical characteristics and the etch properties during subsequent manufacturing processes. Next, the resist mask 106 may be formed on the basis of well-established techniques, including spin coating of a resist material adapted to the respective exposure wavelength, such as 248 nm or 193 nm for sophisticated applications, followed by respective treatments, such as baking and the like. Thereafter, the resist material may be exposed and may be developed in order to form the opening 106A, wherein the ARC 105 may provide the desired optical characteristics while additionally substantially suppressing any adverse effect of nitrogen on the resist material of the mask 106.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage, in which a corresponding contact opening 108 is formed through the ARC 105 and the interlayer dielectric material 104. For this purpose, a corresponding etch sequence 107 may be performed so as to etch through the ARC 105 and through the layer 104B, wherein the corresponding etch step may be reliably controlled on the basis of the contact etch stop layer 104A, which may then be opened in a separate etch step of the process 107.
Thereafter, the etch sequence 107 may comprise a further step in order to remove the resist mask 106 and concurrently remove a portion of the ARC material 105, wherein at least the cap layer 105A may be removed. A corresponding process sequence may be highly advantageous with respect to the overall throughput, since the number of process steps and required process chambers in the etch sequence 107 may be reduced compared to other approaches, in which the resist mask 106 may be removed in a separate step followed by an additional etch process for removing the cap layer 105B and a portion of the layer 105A. After the combined removal of the resist mask 106 and the cap layer 105B in combination with a portion of the layer 105A, the resulting surface of the device 100 may be prepared for the deposition of an appropriate barrier material, required for filling the respective contact opening 108 with an appropriate material, such as tungsten, tungsten silicide and the like.
FIG. 1c schematically illustrates the semiconductor device 100 during a corresponding sputter etch process 109, which may represent an initial phase of a corresponding sputter deposition process, wherein respective surface portions of the contact opening 108 and the exposed contact area 103 are cleaned in order to provide the desired barrier and adhesion characteristics of the material to be deposited. It appears, however, that a corresponding defect rate caused by particle contamination of substrates having formed thereon a semiconductor device 100 according to the manufacturing stage as shown in FIG. 1c may significantly increase after the sputter etch process 109, wherein, additionally, a corresponding increase of the defect rate is observed with an increasing number of substrates processed within a respective sputter etch tool.
FIG. 1d schematically illustrates a corresponding progression over time of a defect rate for a plurality of substrates processed according to the process sequence described with reference to FIGS. 1a-1c, wherein the measurement relates to the point of the process flow after the sputter etch process 109. The vertical axis represents the number of defects per wafer measured, while the horizontal axis represents the number of wafers processed. It is evident that an initially high defect rate after the sputter etch process 109 may be obtained and this defect rate may even significantly increase with the number of substrates processed in the respective sputter etch tool. It is believed that the increasing defect rate may be related to a corresponding contamination of chamber walls of the respective process tool due to ion bombardment of the exposed substrate surface during the sputter etch process 109, which may cause the sputtering off of silicon nitride components, silicon and oxygen, wherein a corresponding material composition may deposit on the chamber walls having a reduced degree of adhesion so that a corresponding probability for flaking off of the wall surfaces may increase with increasing process time of the respective sputter tool. Thus, although a highly efficient process sequence may be established on the process flow described above with respect to throughput, a significant reduction in yield may be observed due to the increasing defect rate after the sputter etch process 109.
It is well known that silicon dioxide, when subjected to a sputter etch process, may also be deposited on chamber walls of respective process chambers, yet with a significantly reduced probability for flaking off, thereby not unduly contributing to an increased defect rate. However, maintaining the silicon dioxide layer 105B during the etch sequence 107 may result in increased process complexity of the corresponding etch sequence. Also, providing an increased thickness of the layer 105B so as to maintain a portion thereof even after the process sequence 107 may significantly deteriorate a corresponding process result in patterning the contact opening 108, thereby rendering this option less desirable.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.